Author:
Badereddine N.,Wang Z.,Girard P.,Chakrabarty K.,Virazel A.,Pravossoudovitch S.,Landrault C.
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference25 articles.
1. Al-Yamani A, Chmelar E, Grinchuck M (2005) Segmented addressable scan architecture. IEEE VLSI Test Symposium, pp 405–411
2. Badereddine N, Girard, Pravossoudovitch S, Landrault C, Virazel A, Wunderlich H-J (2006) Structural power-aware assignment of don’t cares for peak power reduction during scan testing. IFIP International Conference on Very Large Scale Integration, pp 403–408
3. Baik DH, Saluja KK (2005) Progressive random access scan: a simultaneous solution to test power, test data volume and test time. IEEE International Test Conference, paper 15.2
4. Bayraktaroglu I, Orailoglu A (2003) Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression. IEEE VLSI Test Symposium, pp 113–118
5. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing. Kluwer Academic Publishers
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