1. International Technology Roadmap for Semiconductors, http://www.itrs.net/
2. V.V. Zhirnov, R.K. Cavin, J.A. Hutchby, and G.I. Bourianoff, “Limits to binary logic switch scaling: A Gedanken model,” Proc. IEEE 91(11):1934–1939, 2003.
3. T.-J. King, “FinFETs for nanoscale CMOS digital integrated circuits,” Proc. IEEE/ACM Int. Conf. Computer-Aided Design, San Diego, CA, pp. 207–210, 2005.
4. P. Beckett, “A fine-grained reconfigurable logic array based on double-gate transistors,” Proc. IEEE Int. Field-Programmable Technol. Conf., December 16–18, pp. 260–267, 2002.
5. K. Yuen, T. Man, and A.C.K. Chan, “A 2-bit MONOS nonvolatile memory cell based on double-gate asymmetric MOSFET structure,” IEEE Electron. Device Lett. 24:518–520, 2003.