Author:
Garg Rajesh,Khatri Sunil P.
Reference31 articles.
1. H. Chang and S. S. Sapatnekar, “Statistical timing analysis under spatial correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1467–1482, Sept. 2005.
2. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, “First-order incremental block-based statistical timing analysis,” in Proc. of the Design Automation Conf., 2004, pp. 331–336.
3. A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in Proc. of the Intl. Conf. on Computer-Aided Design, Nov. 2003, pp. 900–907.
4. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, “Statistical timing analysis using bounds,” in Proc. of the Conf. on Design Automation and Test in Europe, March.
5. O. Neiroukh and X. Song, “Improving the process-variation tolerance of digital circuits using gate sizing and statistical techniques,” in Proc. of the Conf. on Design Automation and Test in Europe, 2005, pp. 294–299.
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