3D Physical Design
Author:
Cong Jason,Luo Guojie
Reference59 articles.
1. Ababei C, Mogal H, Bazargan K (2005) Three-dimensional place and route for FPGAs. In: Proceedings of the 2005 conference on Asia and South Pacific design automation, Shanghai, China, 18–21 January, pp 773–778 2. Balakrishnan K, Nanda V, Easwar S, Lim SK (2005) Wire congestion and thermal aware 3D global placement. Proceedings of the 2005 conference on Asia and South Pacific design automation, Shanghai, China, 18–21 January, pp 1131–1134 3. Banerjee K, Souri SJ, Kapur P, Saraswat KC (2001) 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. In: Proc IEEE 89(5):602–633 4. Bernstein K, Andry P, Cann J, Emma P, Greenberg D, Haensch W, Ignatowski M, Koester S, Magerlein J, Puri R, Young A (2007) Interconnects in the third dimension: design challenges for 3D ICs. In: Proceedings of the 44th annual conference on design automation, San Diego, California, 04–08 June, pp 562–567 5. Bertsekas DP (1977) Approximation procedures based on the method of multipliers. J Optim Theor Appl 23(4):487–510
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