1. Agarwal A, Blaauw D, Zolotov V 2003 Statistical timing analysis for intra-die process variations with spatial corrections. Proc. Int. Conf. Computer-Aided Design, San Jose, CA 900–907
2. Boning D, Nassif S 2001 Models of process variations in device and interconnect. Design of highperformance microprocessor circuits, 1st ed., A Chandrakasan, W J Bowhill, F Cox (eds). IEEE Press ITRS Interconnect 2006 update
3. Nassif S R 2001 Modelling and analysis of manufacturing variations. IEEE Conference on Custom Integrated Circuits 223–228
4. Usha Narasimha, Binu Abraham, Nagaraj NS 2006 Statistical analysis of capacitance coupling effects on delay and noise. Proc. International Symposium on Quality Electronic Design
5. Vishweswariah C 2003 Death, taxes and failing chips. Proc. Design Automation Conf., Anaheim, CA 343–347