Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-62874-0_7
Reference21 articles.
1. Akbari, O., Kamal, M., Afzali-Kusha, A., Pedram, M., Shafique, M.: X-cgra: An energy-efficient approximate coarse-grained reconfigurable architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39(10) (2019). https://doi.org/10.1109/TCAD.2019.2937738
2. Dai, L., Wang, Y., Liu, C., Li, F., Li, H., Li, X.: Reexamining cgra memory sub-system for higher memory utilization and performance. In: 2022 IEEE 40th International Conference on Computer Design (ICCD). IEEE (2022).https://doi.org/10.1109/ICCD56317.2022.00017
3. Das, S., Martin, K.J., Coussy, P., Rossi, D., Benini, L.: Efficient mapping of cdfg onto coarse-grained reconfigurable array architectures. In: 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE (2017).https://doi.org/10.1109/ASPDAC.2017.7858308
4. Das, S., Martin, K.J., Rossi, D., Coussy, P., Benini, L.: An energy-efficient integrated programmable array accelerator and compilation flow for near-sensor ultralow power processing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38(6) (2018).https://doi.org/10.1109/TCAD.2018.2834397
5. Dave, S., Balasubramanian, M., Shrivastava, A.: Ramp: Resource-aware mapping for cgras. In: Proceedings of the 55th Annual Design Automation Conference (2018).https://doi.org/10.1145/3195970.3196101
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