Simulation and Modelling for Network-on-Chip Based MPSoC
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-42921-7_26
Reference7 articles.
1. Benini, L., Micheli, G.D.: Networks on chips: a new SoC paradigm. Computer 35(1), 70–78 (2002). https://doi.org/10.1109/2.976921
2. Catania, V., Mineo, A., Monteleone, S., Palesi, M., Patti, D.: Noxim: an open, extensible and cycle-accurate network on chip simulator. In: 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 162–163 (2015). https://doi.org/10.1109/ASAP.2015.7245728
3. Herdt, V., Große, D., Pieper, P., Drechsler, R.: RISC-V based virtual prototype: an extensible and configurable platform for the system-level. J. Syst. Archit. 109, 1 October 2020. https://doi.org/10.1016/j.sysarc.2020.101756
4. Haase, J., Gros, A., Feichter, M., Göhringer, D.: Panaca: an open-source configurable network-on-chip simulation platform. In: 2022 35th SBC/SBMicro/ IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1–6 (2022). https://doi.org/10.1109/SBCCI55532.2022.9893260
5. Haase, J., Ali, M., Göhringer, D.: Unlocking the potential of RISC-V heterogeneous MPSoCs: a panaca-based approach to simulation and modeling. In: Embedded Computer Systems: Architectures, Modeling, and Simulation, Springer International Publishing (2023)
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