PANACA: An Open-Source Configurable Network-on-Chip Simulation Platform
Author:
Affiliation:
1. Technische Universität Dresden,Chair of Adaptive Dynamic Systems,Germany
Funder
DFG
Deutsche Forschungsgemeinschaft
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9893151/9893215/09893260.pdf?arnumber=9893260
Reference14 articles.
1. BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass
2. Extensible and Configurable RISC-V Based Virtual Prototype
3. ORION3.0: A Comprehensive NoC Router Estimation Tool
4. Secure communication protocol for network-on-chip with authenticated encryption and recovery mechanism;haase;2022 IEEE 33rd International Conference on Application-specific Systems Architectures and Processors (ASAP),2022
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1. Enhancing Robustness and Reliability of Networks-on-Chip with Network Coding;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31
2. Simulation and Modelling for Network-on-Chip Based MPSoC;Applied Reconfigurable Computing. Architectures, Tools, and Applications;2023
3. Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to Simulation and Modeling;Lecture Notes in Computer Science;2023
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