Three Dimensional Simulation of Filling Process for Stacked-Chip Scale Packages

Author:

Mior Abd Majid Mior Firdaus,Mohamad Sidik Mohamad Sabri,Abu Bakar Muhamad Husaini,Shafee Khairul Shahril,Yusuf Zainal Nazri Mohd,Zain Mohamad Shukri Mohd,Zulkifly Abdullah Mohd.

Publisher

Springer International Publishing

Reference15 articles.

1. Tummala, R.R.: Fundamentals of Microsystems Packaging, pp. 44–79. McGraw Hill, Singapore (2001)

2. Manzione, L.T.: Plastic Packaging of Microelectronic Device, pp. 1–35. Van Nostrand Reinhold, New York (1990)

3. Liang, C.W., Kulakarni, V.M., Aswatha Narayana, P.A., Seetharamu, K.N.: Parametric studies in transfer molding for Newtonian flids. J. Phys. Sci. 16(2), 103–114 (2005)

4. Kulkarni, V.M., Seetharamu, K.N., Azid, I.A., Aswatha Narayana, P.A., Quadir, G.A.: Numerical simulation of underfill encapsulation process based on charecteristic split method. Int. J. Numer. Meth. Engng. 66, 1658–1671 (2006)

5. Kada, M., Smith, L.: Advancements in Stacked Chip Scale Packaging (S-CSP) provides system-in-a-package functionality for wireless and handheld applications. Future Fab. Intl. 9, 246–251 (2000)

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