Application Specific Reconfigurable SoC Interconnection Network Architecture
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-030-18656-2_24
Reference10 articles.
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2. Khan, G.N.: Efficient and low power NoC router architecture. In: Choi, J., Iniewski, K. (eds.) High-Speed and Low Power Technologies: Electronics and Photonics, pp. 211–251. CRC Press, Taylor & Francis (2018)
3. Stensgaard, M., Sparsø, J.: ReNoC: a network-on-chip architecture with reconfigurable topology. In: Proceedings 2nd ACM/IEEE International Symposium Networks-on-Chip (NOCS), Newcastle Upon Tyne, UK, pp. 55–64, April 2008
4. Chen, C.H.O., Park, S., Krishna, T., Subramanian, S., Chandrakasan, A.P., Peh, L.S.: SMART: a single-cycle reconfigurable NoC for SoC applications. In: Proceedings Design Automation and Test in Europe (DATE) Conference, Grenoble, pp. 338–343, March 2013
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1. An analytically derived vectorized model for application graph mapping in interconnection networks;Journal of Ambient Intelligence and Humanized Computing;2022-01-24
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