ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology-Reference-Cited by-同舟云学术

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ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

Published:2008-04 Issue: Volume: Page:
ISSN:
Container-title:Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
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Author:

Stensgaard Mikkel Bystrup,Spars Jens

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4492707/4492708/04492725.pdf?arnumber=4492725

Cited by 70 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Traffic-oriented reconfigurable NoC with augmented inter-port buffer sharing;Frontiers of Information Technology & Electronic Engineering;2024-08-16

2. Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip;Symmetry;2024-01-21

3. RTASS: a RunTime Adaptable and Scalable System for Network-on-Chip-Based Architectures;2023 26th Euromicro Conference on Digital System Design (DSD);2023-09-06

4. Performance Analysis of an Efficient Router using X Y Algorithm;International Journal of Innovative Technology and Exploring Engineering;2023-06-30

5. PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs;Micromachines;2023-02-21

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