Publisher
Springer Nature Switzerland
Reference18 articles.
1. Anderson, J.H., Wang, Q.: Area-efficient FPGA logic elements: architecture and synthesis. In: 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp. 369–375 (2011). https://doi.org/10.1109/ASPDAC.2011.5722215
2. Anderson, S.E.: Bit twiddling hacks (2005). http://graphics.stanford.edu/seander/bithacks.html
3. Chapman, K.: Multiplexer design techniques for Datapath performance with minimized routing resources. Xilinx All Programmable 1, 1–32 (2014)
4. Dimitrakopoulos, G., Galanopoulos, K., Mavrokefalidis, C., Nikolos, D.: Low-power leading-zero counting and anticipation logic for high-speed floating point units. IEEE Trans. Very Large Scale Integr. Syst. 16(7), 837–850 (2008). https://doi.org/10.1109/TVLSI.2008.2000458
5. Dohi, K., Okina, K., Soejima, R., Shibata, Y., Oguri, K.: Performance modeling of stencil computing on a stream-based FPGA accelerator for efficient design space exploration. IEICE Trans. Inf. Syst. 98(2), 298–308 (2015)