Comparators
Author:
Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-90808-9_12
Reference45 articles.
1. W-Y. Lee, L-S. Kim, An adaptive equalizer with the capacitance multiplication for displayport main link in 0.18-μm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20, 964–968 (2012)
2. S.-K. Shin, J.C. Rudell, D.C. Daly, C.E. Munoz, D.-Y. Chang, K. Gulati, H.-S. Lee, M.Z. Straayer, A 12-bit 200-MS/s zero-crossing-based pipelined ADC with early sub-ADC decision and output residue background calibration. IEEE J. Solid-State Circuits 49, 1366–1382 (2014)
3. P. Nuzzo, F. De Bernardinis, P. Terreni, G. Van der Plas, Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans. Circuits Syst. I: Regul. Pap. 55, 1441–1454 (2008)
4. B. Razavi, The strongARM latch [a circuit for all seasons]. IEEE Solid-State Circuits Mag. 7, 12–17 (2015)
5. J.P. Keane et al., An 8 GS/s time-interleaved SAR ADC with unresolved decision detection achieving − 58 dBFS noise and 4 GHz bandwidth in 28 nm CMOS, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers (2017), pp. 284–285
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