Author:
Martínez Víctor,Serpa Matheus S.,Pavan Pablo J.,Padoin Edson Luiz,Navaux Philippe O. A.
Publisher
Springer International Publishing
Reference26 articles.
1. Breuer, A., Heinecke, A., Bader, M.: Petascale local time stepping for the ADER-DG finite element method. In: 2016 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2016, Chicago, IL, USA, 23–27 May 2016, pp. 854–863 (2016)
2. Buchty, R., Heuveline, V., Karl, W., Weiss, J.P.: A survey on hardware-aware and heterogeneous computing on multicore processors and accelerators. Concurrency Comput. Pract. Exp. 24(7), 663–675 (2012).
https://doi.org/10.1002/cpe.1904
3. Christen, M., Schenk, O., Burkhart, H.: Automatic code generation and tuning for stencil kernels on modern shared memory architectures. Comput. Sci. 26(3–4), 205–210 (2011)
4. Cronsioe, J., Videau, B., Marangozova-Martin, V.: Boast: bringing optimization through automatic source-to-source transformations. In: 2013 IEEE 7th International Symposium on Embedded Multicore SoCs, pp. 129–134, September 2013.
https://doi.org/10.1109/MCSoC.2013.12
5. Datta, K., Kamil, S., Williams, S., Oliker, L., Shalf, J., Yelick, K.: Optimization and performance modeling of stencil computations on modern microprocessors. SIAM Rev. 51(1), 129–159 (2009).
https://doi.org/10.1137/070693199