In-Memory Computing for AI Accelerators: Challenges and Solutions-Reference-Cited by-同舟云学术

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In-Memory Computing for AI Accelerators: Challenges and Solutions

Published:2023-10-01 Issue: Volume: Page:199-224
ISSN:
Container-title:Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing
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Author:

Krishnan Gokul,Mandal Sumit K.,Chakrabarti Chaitali,Seo Jae-sun,Ogras Umit Y.,Cao Yu

Publisher

Springer International Publishing

Link

https://link.springer.com/content/pdf/10.1007/978-3-031-19568-6_7

Reference117 articles.

1. Agarwal, N., Krishna, T., Peh, L.S., Jha, N.K.: GARNET: A Detailed on-chip Network Model inside a Full-system Simulator. In: 2009 IEEE International Symposium on Performance Analysis of Sand Software, pp. 33–42 (2009)

2. Arka, A.I., Doppa, J.R., Pande, P.P., Joardar, B.K., Chakrabarty, K.: ReGraphX: NoC-enabled 3D heterogeneous ReRAM architecture for training graph neural networks. In: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1667–1672. IEEE (2021)

3. Arka, A.I., Joardar, B.K., Doppa, J.R., Pande, P.P., Chakrabarty, K.: DARe: DropLayer-aware manycore ReRAM architecture for training graph neural networks. In: 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–9 (2021)

4. Arka, A.I., Joardar, B.K., Doppa, J.R., Pande, P.P., Chakrabarty, K.: Performance and accuracy tradeoffs for training graph neural networks on ReRAM-based architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 29(10), 1743–1756 (2021)

5. Bharadwaj, S., Yin, J., Beckmann, B., Krishna, T.: Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling. In: 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1–6. IEEE (2020)

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