Case Study: Real Hardware-Software Design of 3D-NoC-Based Neuromorphic System
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-92525-3_8
Reference33 articles.
1. Ahmed AB, Abdallah AB (2014) Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures. J Parallel Distrib Comput 74(4):2229–2240
2. Akopyan F et al (2015) TrueNorth: Design and tool flow of a 65 mW 1 million neuron programmable neurosynaptic chip. IEEE Trans Comput Aided Des Integr Circuits Syst 34(10):1537–1557
3. Banerjee K et al (2001) 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc IEEE 89(5):602–633
4. Ben Abdallah A, Dang KN (2021) Toward robust cognitive 3d brain-inspired cross-paradigm system. Frontiers Neurosci 15:795
5. Ben Ahmed A, Ben Abdallah A (2013) Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC). J Supercomput 66(3):1507–1532
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