Generic Architecture of Deterministic Completion Detection Scheme
Author:
Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-18397-3_5
Reference6 articles.
1. Lai, K. K. (2016), Novel Asynchronous Completion Detection For Arithmetic Datapaths, Taylor’s University, Malaysia.
2. Nowick, S. M. (1996), ‘Design of a low-latency asynchronous adder using speculative completion’, IEE Proceedings-Computers and Digital Techniques 143(5), 301–307.
3. Koes, D., Chelcea, T., Onyeama, C. and Goldstein, S. C. (2005), Adding faster with application specific early termination, Technical report, Carnegie-Mellon Univ Pittsburgh PA publisher of Computer Science.
4. Bhattacharjee, P., Bhattacharyya, B. and Majumder, A. (2021), ‘A vector-controlled variable delay circuit to develop near-symmetric output rise/fall time’, Circuits, Systems, and Signal Processing 40, 1569–1588.
5. Srivastava, P., Chung, E. and Ozana, S. (2020), ‘Asynchronous floating-point adders and communication protocols: A survey’, Electronics 9(10), 1687.
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