Design and Implementation of Modified Vedic Multiplier Using Modified Decoder-Based Adder
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-20429-6_20
Reference19 articles.
1. Krishna, A.V., Deepthi, S., Devi, M.N.: Design of 32-bit mac unit using Vedic multiplier and XOR logic. In: Proceedings of International Conference on Recent Trends in Machine Learning, IoT, Smart Cities and Applications, pp. 715–723. Springer (2021)
2. O’Connor, M., Swartzlander, E.E.: Exploiting asymmetry in booth-encoded multipliers for reduced energy multiplication. In: 2015 49th Asilomar Conference on Signals, Systems and Computers, pp. 722–726. IEEE (2015)
3. Saravanan, S., Madheswaran, M.: Design of hybrid encoded booth multiplier with reduced switching activity technique and low power 0.13 µm adder for DSP block in wireless sensor node. In: 2010 International Conference on Wireless Communication and Sensor Computing (ICWCSC), pp. 1–6. IEEE (2010)
4. Saravanan, S., Madheswaran, M.: Design of low power multiplier with reduced spurious transition activity technique for wireless sensor network. In: 2008 Fourth International Conference on Wireless Communication and Sensor Networks, pp. 36–39. IEEE (2008)
5. Ram, C.G., Lakshmanna, Y.R., Rani, D.S., Sindhuri, K.B.: Area efficient modified Vedic multiplier. In: 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), pp. 1–5. IEEE (2016)
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