Radiation Hardness by Design Techniques for 1 Grad TID Rad-Hard Systems in 65 nm Standard CMOS Technologies

Author:

Ciarpi Gabriele,Saponara Sergio,Magazzù Guido,Palla Fabrizio

Publisher

Springer International Publishing

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments;Electronics;2024-02-13

2. 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

3. Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit;Japanese Journal of Applied Physics;2023-01-31

4. Generic Analog 8 Bit DAC IP Block in 28nm CMOS for the High Energy Physics Community;2022 Austrochip Workshop on Microelectronics (Austrochip);2022-10-11

5. Total ionizing dose effect on 2-D array data transfer ICs designed and fabricated by 0.18 μm CMOS technology;Japanese Journal of Applied Physics;2022-03-30

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