FPGAs in Supercomputers: Performance Through Dataflow Programming and Flexibility
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-31209-0_25
Reference8 articles.
1. Vaishnav, A., et al.: Heterogeneous resource-elastic scheduling for CPU+ FPGA architectures. In: Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, pp. 1–6 (2019)
2. Flynn, M.J.: Dataflow computing for data-intensive applications (2011)
3. Gurd, J.R., Kirkham, C.C., Watson, I.: The Manchester prototype dataflow computer. Commun. ACM 28(1), 34–52 (1985)
4. Jia, Q., Zhou, H.: Tuning stencil codes in OpenCL for FPGAs. In: 2016 IEEE 34th International Conference on Computer Design (ICCD), pp. 249–256. IEEE (2016)
5. Johnston, W.M., Hanna, J.R.P., Millar, R.J.: Advances in dataflow programming languages. ACM Comput. Surv. (CSUR) 36(1), 1–34 (2004)
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