Accurate High Level Resources and Power Estimators for FPGAs-Reference-Cited by-同舟云学术

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Accurate High Level Resources and Power Estimators for FPGAs

Published:2019-08-02 Issue: Volume: Page:111-123
ISSN:2190-3018
Container-title:Smart Innovation, Systems and Technologies
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Author:

Mami Sonia,Lahbib Younes,Hachaïchi Yassine

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-21009-0_10

Reference11 articles.

1. Gasmi, K., Rebaya, A., Amari, I., Hasnaoui, S.: Workflow for multi-core architecture: from Matlab/Simulink models to hardware mapping/scheduling. In: 7th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT), pp. 142–148 (2016)

2. Meeuws, R., Ostadzadeh, S.A., Galuzzi, C., Sima, V.M., Nane, R., Bertels, K.: Quipu: a statistical model for predicting hardware resources. ACM Trans. Reconfigurable Technol. Syst. Article No. 3 (2013)

3. Deng, L., Sobti, K., Chakrabarti, C., Zhang, Y.: Accurate area, time and power models for FPGA-based implementations. J. Signal Process. Syst. 63, 39–50 (2011)

4. Chuong, L.M., Lam, S.-K., Srikanthan, T.: Area-time estimation of controller for porting C-based functions onto FPGA. In: Proceedings of the RSP 2009, pp. 145–151 (2009)

5. Cilardo, A., Durante, P., Lofiego, C., Mazzeo, A.: Early prediction of hardware complexity in HLL-to-HDL translation. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), pp. 483–488 (2010)

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Web-based Calculator Tool for FPGA Power Consumption Estimation for Teaching Purposes;2023 International Conference on Electromechanical and Energy Systems (SIELMEN);2023-10-11

2. A SoPC FPGA Implementing of an Enhanced Parallel CFAR Architecture;2022 IEEE 9th International Conference on Sciences of Electronics, Technologies of Information and Telecommunications (SETIT);2022-05-28

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