Multi-clusters: An Efficient Design Paradigm of NN Accelerator Architecture Based on FPGA
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-21395-3_14
Reference24 articles.
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2. Dhouibi, M., Ben Salem, A.K., Saidi, A., Ben Saoud, S.: Accelerating deep neural networks implementation: a survey. IET Comput. Digit. Tech. 15(2), 79–96 (2021)
3. Geng, T., Wang, T., Sanaullah, A., Yang, C., Patel, R., Herbordt, M.: A framework for acceleration of CNN training on deeply-pipelined FPGA clusters with work and weight load balancing. In: 2018 28th International Conference on Field Programmable Logic and Applications (FPL), pp. 394–3944. IEEE (2018)
4. Gokhale, V., Zaidy, A., Chang, A.X.M., Culurciello, E.: Snowflake: an efficient hardware accelerator for convolutional neural networks. In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–4. IEEE (2017)
5. Gong, L., Wang, C., Li, X., Chen, H., Zhou, X.: MALOC: a fully pipelined FPGA accelerator for convolutional neural networks with all layers mapped on chip. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 37(11), 2601–2612 (2018). https://doi.org/10.1109/TCAD.2018.2857078
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