Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices-Reference-Cited by-同舟云学术

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Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices

Published:2024 Issue: Volume: Page:193-209
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:en
Short-container-title:

Author:

Babaei Bardia^ORCID,Koch Dirk^ORCID

Publisher

Springer Nature Switzerland

Link

https://link.springer.com/content/pdf/10.1007/978-3-031-55673-9_14

Reference19 articles.

1. Agarwal, K., Nassif, S.: Characterizing process variation in nanometer CMOS. In: Proceedings of the 44th Annual Design Automation Conference, DAC 2007, pp. 396–399. Association for Computing Machinery, New York (2007)

2. Babaei, B., Koch, D.: Precise characterizing of FPGAs in production systems. In: 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), pp. 464–465 (2022)

3. Babaei, B., Koch, D.: Tunable fine-grained clock phase-shifting for FPGAs. In: 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), pp. 384–390 (2022)

4. Baravelli, E., Dixit, A., Rooyackers, R., Jurczak, M., Speciale, N., Meyer, K.D.: Impact of line-edge roughness on FinFET matching performance. IEEE Trans. Electron Devices 54, 2466–2474 (2007). https://api.semanticscholar.org/CorpusID:25864162

5. Dargar, S.K., Srivastava, V.M.: Performance analysis of 10 nm FinFET with scaled fin-dimension and oxide thickness. In: 2019 International Conference on Automation, Computational and Technology Management (ICACTM), pp. 1–5 (2019)

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1. Ph.D. Project: ManAge: A Tool for Timing Characterization of FPGAs;2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2024-05-05

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