1. Sutaria, K., Ramkumar, A., Zhu, R., Rajveev, R., Ma, Y., & Cao, Y. (2014). BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation. In 51st ACM/EDAC/IEEE Design Automation Conference (DAC) (pp. 1–6). IEEE.
2. Duhan, P., Rao, V. R., & Mohapatra, N. R. (2017). PBTI in HKMG nMOS transistors—effect of width, layout, and other technological parameters. IEEE Transactions on Electron Devices, 64(10), 4018–4024.
3. Fang, J., & Sapatnekar, S. S. (2013). The impact of BTI variations on timing in digital logic circuits. IEEE Transactions on Device and Materials Reliability 13(1), 277–286.
4. Kumar, S. V., Kim, C. H., & Sapatnekar, S. S. (2007). NBTI-aware synthesis of digital circuits. In Proceedings of the 44th Annual Design Automation Conference (pp 370–375). ACM.
5. Wu, K. C., & Marculescu, D. (2009). Joint logic restructuring and pin reordering against NBTI-induced performance degradation. In Proceedings of the Conference on Design, Automation and Test in Europe (pp. 75–80). European Design and Automation Association.