Analog In-Memory Computing with SOT-MRAM: Architecture and Circuit Challenges
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-91741-8_3
Reference14 articles.
1. J. Doevenspeck, K. Garello, B. Verhoef, R. Degraeve, S.V. Beek, D. Crotti, F. Yasin, S. Couet, G. Jayakumar, I.A. Papistas, P. Debacker, R. Lauwereins, W. Dehaene, G. Kar, S. Cosemans, A. Mallik, D. Verkest, SOT-MRAM based analog in-memory computing for DNN inference, in IEEE symposium on VLSI technology (Honolulu, HI, USA, 2020)
2. I.A. Papistas, S. Cosemans, B. Rooseleer, J. Doevenspeck, M.-H. Na, A. Mallik, P. Debacker, D. Verkest, A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-memory analog matrix-vector-multiplier for DNN acceleration, in IEEE custom integrated circuits conference (CICC) (2021)
3. D. Bankman, J. Messner, A. Gural, B. Murmann, RRAM-based in-memory computing for embedded deep neural networks, in IEEE asilomar conference on signals, systems & computers (Pacific Grove, CA, USA, 2019)
4. S. Cosemans, B. Verhoef, J. Doevenspeck, I.A. Papistas, F. Catthoor, P. Debacker, A. Mallik, D. Verkest, Towards 10000TOPS/W DNN inference with analog in-memory computing—a circuit blueprint, device options and requirements, in IEEE international electron devices meeting (IEDM) (San Francisco, CA, USA, 2019)
5. J. Doevenspeck, R. Degraeve, S. Cosemans, P. Roussel, B.-E. Verhoef, R. Lauwereins, W. Dehaene, Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications, in 48th European solid-state device research conference (ESSDERC) (Dresden, Germany, 2018)
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