Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-030-79025-7_18
Reference11 articles.
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3. Dhar, A., et al.: FReaC cache: folded-logic reconfigurable computing in the last level cache. In: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
4. Lin, T.J., et al.: A fine-grain dynamically reconfigurable architecture aimed at reducing the FPGA-ASIC gaps. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(12), 2607–2620 (2014)
5. Reagen, B., et al.: MachSuite: benchmarks for accelerator design and customized architectures. In: 2014 IEEE International Symposium on Workload Characterization (2014)
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