Analog Implementation of Neural Network
Author:
Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-27609-5_9
Reference13 articles.
1. Jie, L.S., Ruslan, S.H.: A 4$$\times $$4 bit vedic multiplier with different voltage supply in 90 nm CMOS technology. Int. J. Integr. Eng. 9, 114–117 (2017)
2. Ghomi, A., Dolatshahi, M.: Design of a new CMOS low-power analogue neuron. IETE J. Res. 64, 1–9 (2017). https://doi.org/10.1080/03772063.2017.1351315
3. Santiago, A.M., Hernández-Gracidas, C., Rosales, L.M., Algredo-Badillo, I., García, M., Orozco-Torres, M.C.: CMOS implementation of ANNs based on analog optimization of n-dimensional objective functions implementation of anns based on analog optimization of n-dimensional objective functions. Sensors 21, 7071 (2021). https://doi.org/10.3390/s21217071
4. Hasan, R., Taha, T.M., Yakopcic, C.: On-chip training of memristor based deep neural networks. In: 2017 International Joint Conference on Neural Networks (IJCNN), pp. 3527–3534 (2017). https://doi.org/10.1109/IJCNN.2017.7966300
5. Krestinskaya, O., Salama, K.N., James, A.P.: Learning in memristive neural network architectures using analog backpropagation circuits. IEEE Trans. Circ. Syst. I: Regular Papers 66(2), 719–732 (2019). https://doi.org/10.1109/TCSI.2018.2866510
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