On-chip training of memristor based deep neural networks

Author:

Hasan Raqibul,Taha Tarek M.,Yakopcic Chris

Publisher

IEEE

Cited by 32 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Hybrid CMOS-Memristor synapse circuits for implementing Ca ion-based plasticity model;Scientific Reports;2024-08-02

2. Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

3. Performance comparison of memristor crossbar-based analog and FPGA-based digital weight-memory-less neural networks;2023 IEEE International Conference on Rebooting Computing (ICRC);2023-12-05

4. ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12

5. Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

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