Iterative Application Mapping with TSV Placement Strategy for Design a 3D NoC-Based Multi-Core Systems
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-030-31310-4_3
Reference18 articles.
1. Bahmani, M., Sheibanyrad, A., Petrot, F., Dubois, F., & Durante, P. (2012). A 3D-NoC router implementation exploiting vertically-partially-connected topologies. In Proceedings of Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 9–14).
2. Chang, K. C., & Chen, T. F. (2008). Low-power algorithm for automatic topology generation for application-specific networks-on-chips. IET Computers and Digital Techniques, 2(3), 239–249.
3. Dubois, F., Sheibanyrad, A., Petrot, F., & Bahmani, M. (2013). Elevator-first: A deadlock-free distributed routing algorithm for vertically partially connected 3D-NoCs. IEEE Transactions on Computers, 62(3), 609–615.
4. Feero, B. S., & Pande, P. P. (2009). Networks-on-Chip in a three dimensional environment: A performance evaluation. IEEE Transactions on Computers, 58(1), 32–45.
5. Kernighan, B., & Lin, S. (1970). An efficient heuristic procedure for partitioning graphs. Bell System Technical Journal, 49(2), 291–307.
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