Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields-Reference-Cited by-同舟云学术

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Rectification of Arithmetic Circuits with Craig Interpolants in Finite Fields

Published:2019 Issue: Volume: Page:79-106
ISSN:1868-4238
Container-title:VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms
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Author:

Gupta Utkarsh,Ilioaea Irina,Rao Vikas,Srinath Arpitha,Kalla Priyank,Enescu Florian

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-23425-6_5

Reference43 articles.

1. Ritirc, D., Biere, A., Kauers, M.: Column-wise verification of multipliers using computer algebra. In: Formal Methods in Computer-Aided Design (FMCAD), pp. 23–30 (2017)

2. Ciesielski, M., Yu, C., Brown, W., Liu, D., Rossi, A.: Verification of gate-level arithmetic circuits by function extraction. In: 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–6 (2015)

3. Sayed-Ahmed, A., Große, D., Kühne, U., Soeken, M., Drechsler, R.: Formal verification of integer multipliers by combining Gröbner basis with logic reduction. In: Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1048–1053 (2016)

4. Lecture Notes in Computer Science;O Wienand,2008

5. Shekhar, N., Kalla, P., Enescu, F.: Equivalence verification of polynomial datapaths using ideal membership testing. IEEE Trans. CAD 26(7), 1320–1330 (2007)

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1. Logic Synthesis from Polynomials with Coefficients in the Field of Rationals;2023 IEEE 53rd International Symposium on Multiple-Valued Logic (ISMVL);2023-05

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