Publisher
Springer International Publishing
Reference16 articles.
1. El-Chammas M (2017) Design techniques for multi-GS/s and high performance pipelined ADCs. ISSCC F6: Pushing the performance limit in data converters
2. El-Chammas M (2010) Background calibration of timing skew in time-interleaved A/D converters. PhD thesis, Stanford University
3. El-Chammas M, Li X, Kimura S, Maclean K, Hu J, Weaver M, Gindlesperger M, Kaylor S, Payne R, Sestok CK, Bright W (2014) A 12 bit 1.6 GS/s BiCMOS 2 $$\times $$ 2 hierarchical time-interleaved pipeline ADC. IEEE J Solid-State Circuits 49(9):1876–1885
4. Da Dalt N, Harteneck M, Sandner C, Wiesbauer A (2002) On the jitter requirements of the sampling clock for analog-to-digital converters. IEEE Trans Circuits Syst I: Fundam Theory Appl 49(9):1354–1360
5. Tsividis Y (2010) Event-driven data acquisition and digital signal processing-a tutorial. IEEE Trans Circuits Syst II Express Briefs 57(8):577–581