Publisher
Springer International Publishing
Reference14 articles.
1. International Technology Roadmap for Semiconductors, 2013 Edition, Semiconductor Industry Association (SIA), San Jose, CA.
2. K. Fischer et al., “Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14 nm high volume manufacturing,” IEEE International Interconnect Technology Conference, 2015, pp. 5–8, doi: https://doi.org/10.1109/IITC-MAM.2015.7325600.
3. K. Bhattacharya and N. Ranganathan, “A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations,” 10th International Symposium on Quality Electronic Design, 2009, pp. 388–393, doi: https://doi.org/10.1109/ISQED.2009.4810326.
4. N. Kanekawa, E. H. Ibe, T. Suga and Y. Uematsu, “Power Integrity” in Dependability in Electronic Systems, New York, NY, USA: Springer, pp. 91–142, 2011.
5. JM Rabaey, AP Chandrakasan, B Nikolić, Digital integrated circuits: a design perspective, 2nd ed., Pearson Education, 2003.