Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories

Author:

Ishitobi Yuriko,Ishihara Tohru,Yasuura Hiroto

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modelling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Reference22 articles.

1. Segars, S. (2001). Low power design techniques for microprocessors. ISSCC Tutorial Note, February.

2. ARM Ltd. (2008). ARM processor core overview. http://www.arm.com/products/CPUs/ .

3. Montanaro, J., et al. (1996). A 160 MHz, 32b 0.5W CMOS RISC microprocessor. In Proc. of ISSCC, February.

4. Su, C., & Despain, A. (1995). Cache design trade-offs for power and performance optimization: A case study. In Proc. of ISLPED (pp. 63–68), August.

5. Hicks, P., Walnock, M., & Owens, R. M. (1997). Analysis of power consumption in memory hierarchies. In Proc. of ISLPED (pp. 239–242), August.

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