Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Author:

Lin Cheng-Yen,Kuan Chi-Bang,Shih Wen-Li,Lee Jenq Kuen

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Reference38 articles.

1. Macii, E., Pedram, M., Somenzi, F. (1998). High-level power modeling, estimation, and optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(11), 1061–1079.

2. You, Y.p., Lee, Chingren, Lee, J.K. (2002). Compiler analysis and supports for leakage power reduction on microprocessors. In Proceedings of the 15th International Workshop on Languages and Compilers for Parallel Computing(LCPC’02).

3. Chang, J.-M., & Pedram, M. (1995). Register allocation and binding for low power. In DAC ’95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, (pp. 29–35).

4. Lee, C., Lee, J.K., Hwang, T., Tsai, S.-C. (2003). Compiler optimization on vliw instruction scheduling for low power. ACM Transactions on Design Automation of Electronic Systems, 8(2), 252–268.

5. You, Y.-P., Huang, C.-W., Lee, J.K. (2007). Compilation for compact power-gating controls. ACM Transactions on Design Automation of Electronic Systems (TODAES), 12(4), 51.

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