REDUCING THE CONSEQUENCES OF THE WIRE INTERCONNECTIONS IN INTEGRATED CIRCUITS BY OPTIMIZING THE CLOCK TREE-Reference-Cited by-同舟云学术

REDUCING THE CONSEQUENCES OF THE WIRE INTERCONNECTIONS IN INTEGRATED CIRCUITS BY OPTIMIZING THE CLOCK TREE

Published:2023 Issue: Volume: Page:
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Author:

ABGARYAN G.A.,GALSTYAN A.A.,HARUTYUNYAN G.A.

Abstract

With the development of integrated circuits in recent years, the role of interconnec¬t¬i¬o¬ns between wires in them cannot be ignored, because it leads to functional errors of the circuit. A method has been developed that allows to take into account the effects of interconnections during the clock tree synthesis. The interconnection phenomena in memory testing systems are examined and reduced by enhancing the testing system's clock tree.

Publisher

National Polytechnic University of Armenia

Subject

Economics and Econometrics,Energy Engineering and Power Technology,Fuel Technology,Renewable Energy, Sustainability and the Environment,Ophthalmology,Surgery

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