IBIS MODEL ACCURACY IMPROVEMENT USING VARIABLE STEP

Abstract

In all times of integrated circuits (IC) manufacturing, the speed of getting the product on the market has been the main problem for all manufacturers. The main reason for late products has always been the speed of the tools that carry out the testing. The main simulator used by every manufacturer is the SPICE simulator, but with the SPICE simulator it can take up to months to simulate the whole TXRX macro. But since the 1990s with the introduction of the I/O Buffer Information Specification (IBIS) models, the testing time has decreased dramatically. A method is proposed to generate IBIS models with a variable step, that will help to increase the accuracy of the IBIS model during signal integrity (SI) simulations and will correlate with SPICE simulations better. The proposed method can be implemented for all types of TX drivers and IBIS models.