Chip Package Interaction Study to Analyze the Mechanical Integrity of a 3-D TSV Package

Abstract

The convergence and miniaturization of computing and communications dictates building up rather than out. As planar device miniaturization continues to its ultimate limits, the complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation [1]. As the consumers demand more functions on their hand-held electronic devices, the need for more devices such as memory, CPU and GPU in hand-held type footprints is increasing. Chip-stacking (3-D) is emerging as a powerful tool that satiates such IC package requirements. A 3-D FPGA would overcome the interconnect limitations, resulting in greater silicon efficiency per function (number of used gates/total number of gates), faster signal/data throughput, and faster switching of the gate-level configuration. 3-D through-silicon-via (TSV) technology is being termed as the “next big thing” in the semiconductor arena and has the potential of revolutionizing the packaging industry but it has some inherent issues that need to be addressed before it could be implemented in the mainstream electronics industry. TSV fabrication process, thermal management of 3-D TSV packages, TSV joule heating, and chip package interaction (CPI), are some of the key issues in this technology [2, 3, 4, 5, 6]. In this paper, the thermo-mechanical chip-package-interaction (CPI) analysis is carried out and a full field compact 3D modeling methodology has been leveraged to assess the mechanical integrity of a 2 die 3D TSV package during attachment to substrate. This modeling methodology would provide damage predictions caused due to global and local CTE mismatch between the different package components. Mechanical interaction at the Si/TSV regions, back-end Cu/low-k stack, and the inter die μ-bumps during chip attachment is demonstrated in this paper.