Cohesive Zone Models to Predict Multiple White Bumps in Flip-Chip Assemblies

Abstract

The drive towards increased functional integration and improved performance in microelectronic devices has led to the introduction of more layers and porous dielectric materials in back end of line (BEOL) stack. These materials have low mechanical strength as well as adhesive strength and thus, interfacial delamination is a major reliability concern for modern microelectronic devices. In this work, we present a cohesive zone element based finite-element model to predict failures observed at the end of flip-chip assembly reflow process. During lead-free flip-chip assembly, thermo-mechanical stresses arise due to the coefficient of thermal expansion (CTE) mismatch between the organic substrate and the silicon die. Such stresses can be high enough to cause cracking of interlayer dielectric layers present in the vicinity of solder bump. In order to predict such failures, mixed mode cohesive zone parameters are first extracted from interfacial fracture characterization experiments of real-life BEOL stacks. Then, the characterized cohesive zone elements are embedded in 2D finite-element models of flip-chip assembly to predict the failure region. The predicted failure region is compared against 2D fracture mechanics based models as well as failure analysis experiment results. Cohesive zone elements are then implemented over multiple bumps to examine simultaneous failure of multiple bumps under reflow assembly, and thus, the effectiveness of cohesive zone elements compared to fracture mechanics approach is demonstrated.