Auto-Labeling for Pattern Recognition of Wafer Defect Maps in Semiconductor Manufacturing

Abstract

Abstract In practical semiconductor processes, the defect analysis for wafer map is a critical step for improving product quality and yield. These defect patterns can provide important process information so that the process engineers can identify the key cause of process anomalies. However, in supervised learning, the manual annotation for wafer maps is an extremely exhausting task, and it can also induce misjudgment when a long-term operation is implemented. Toward this end, this paper proposes a new auto-labeling system based on ensemble classification. The noted VGG16 model is used in ensemble learning as the building block to train the classifier via a limited number of labeled data. Through the model being trained, the auto-labeling procedure is executed to annotate abundant unlabeled data. Therefore, the classification performances between the models trained by supervised and semi-supervised learning can be compared. In addition, the gradient-weighted class activation mapping (Grad-CAM) is also adopted to analyze and verify the quality of auto-labeling by visual inspection. Based on the experimental results, the proposed auto-label system can return a satisfactory classification performance, and then, the manual labeling operation can be drastically reduced. The classification performance for wafer defect patterns can be further assured as the auto-labeled data are given with corresponding confidence scores of specific defect patterns being identified in this study.