Process-Recipe Development for Printing of Multilayer Circuitry With Z-Axis Interconnects Using Aerosol-Jet Printed Dielectric Vias

Author:

Lall Pradeep1,Narangaparambil Jinesh1,Soni Ved1,Miller Scott2

Affiliation:

1. Department of Mechanical Engineering, NSF-CAVE3 Electronics Research Center, Auburn University, Auburn, AL 36849

2. NextFlex Manufacturing Institute, San Jose, CA 95131

Abstract

Abstract Flexible electronics is emerging as a new consumer-industry phenomenon. The promise of additively printed flexible electronics has sparked interest in a detailed understanding of the parameters and interactions of the printing process with the realized performance. Aerosol Jet printing technology has garnered increased interest, owing to a noncontact nature of print process and the high standoff allowing for printing on nonplanar surfaces. Prior efforts with aerosol-jet printing have focused on single-layer substrates. The current efforts focus on higher end printed circuit boards designs, which may need multilayers, with multilayer stacking of interconnections and z-axis connections through vias. The results presented in the paper attempt to address the need for process recipes for multilayer circuits and z-axis interconnects. Aerosol printing method has been shown to have wide compatibility with wide array of inks such as silver, copper, and carbon. Realization of high-volume scale-up of the process needs process recipes with statistical assessment of process stability and variance. In this paper, z-axis interconnects have been realized with the help of Aerosol printable silver ink and dielectric polyimide ink. The interaction of the sintering profile and the realized conductivity and shear load value of the printed conductive metal layers has been presented for each of the additional layers. Additive build-up processes may need successive exposure to temperature for the purpose of sintering. The downstream-printed conductive lines would undergo different sintering conditions and would then be tested for parameters such as interconnect resistance and shear load to failure. This paper explores the printing of multilayer up to eight conductive layers. Sintering profile for lower resistance per unit length and higher shear load to failure was tested.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Reference21 articles.

1. Screen Printing of Multilayered Hybrid Printed Circuit Boards on Different Substrates;IEEE Trans. Compon., Packag. Manuf. Technol.,2015

2. Robust Design and Design Automation for Flexible Hybrid Electronics,2017

3. How to Make Reliable, Washable, and Wearable Textronic Devices;Sensors,2017

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