Effect of Underfill Thermomechanical Properties on Thermal Cycling Fatigue Reliability of Flip-Chip Ball Grid Array
Author:
Wang Tong Hong1, Lai Yi-Shao1, Wu Jenq-Dah1
Affiliation:
1. Stress-Reliability Lab, Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Road, Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan
Abstract
Plane two-dimensional finite element analysis was applied to study the effect of underfill thermomechanical properties on the potential of thermal fatigue failure for flip-chip ball grid array. Two-stage as well as constant thermomechanical properties of underfills were manipulated to represent extremes of practical underfills. The steady-state creep model was incorporated for the eutectic solder bump to represent its real behavior. It was found from the parametric studies that the underfill with high Young’s modulus, low coefficient of thermal expansion, and high glass transition temperature leads to the longest service life.
Publisher
ASME International
Subject
Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials
Reference10 articles.
1. Popelar, S., and Roesch, M., 2000, “Flip Chip Reliability Modeling Based on Solder Fatigue as Applied to Flip Chip on Laminate Assemblies,” Int. J. Microcircuits Electron. Packag., 23(4), pp. 462–468. 2. Zahn, B. A., 2000, “Comprehensive Solder Fatigue and Thermal Characterization of a Silicon Based Multi-Chip Module Package Utilizing Finite Element Analysis Methodologies,” Proc. 9th International ANSYS Conference Exhibit, 9th International ANSYS Conference and Exhibitions, Pittsburgh, PA, USA. 3. Wiese, S., Schubert, A., Walter, H., Dudek, R., Feustel, F., Meusel, E., and Michel, B., 2001, “Constitutive Behaviour of Lead-Free Solders vs. Lead-Containing Solders Experiments on Bulk Specimens and Flip-Chip Joints,” Proc. 51st Electr. Comp. Technol. Conference, 51st Electronic Components and Technology Conference, Lake Buena Vista, CA, USA, pp. 890–902. 4. Darveaux, R. , 2002, “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation and Fatigue Life Prediction,” J. Electron. Packag., 124(3), pp. 147–154. 5. Lau, J. H., Lee, S. W. R., Pan, S. H., and Chang, C., 2002, “Nonlinear-Time-Dependent Analysis of Micro Via-in-Pad Substrates for Solder Bumped Flip Chip Applications,” J. Electron. Packag., 124, pp. 205–211.
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