1. Advances in Wire Bonding Technology for High Lead Count;IEEE Trans. Compon., Hybrids, Manuf. Technol.,1988
2. Wire-Bonding Process Development for Low-K Materials;J. Microelectron. Eng.,2005
3. Shen, L., Gumaste, V., Poddar, A., and Nguyen, L., 2006, “Effect of Pad Stacks on Dielectric Layer Failure During Wire Bonding,” IEEE 56th Proceedings of Electronic Components and Technology Conference (ECTC), San Diego, CA, May 30–June 2, p. 6.10.1109/ECTC.2006.1645638
4. Failure Estimation of Semiconductor Chip During Wire Bonding Process;ASME J. Electron. Packag.,1999
5. Shu, B., 1991, “Fine Pitch Wire Bonding Development Using a New Multipurpose, Multi-Pad Pitch Test Die,” IEEE 41st Proceedings of Electronic Component and Technology Conference (ECTC), Atlanta, GA, May 11–16, pp. 511–518.10.1109/ECTC.1991.163925