Viscoelastic Warpage Analysis of Surface Mount Package

Abstract

The reduction of the warpage of LSI package is a critical issue to ensure good solder joint connection in surface mount. In this study, different combinations of finite element and calculating methods were used to investigate the best method for predicting the thin small outline packages (TSOP) warpage. The results indicate that viscoelastic-GK calculation with relaxation of shear modulus and of bulk modulus using the multilayer shell element is the most appropriate method for predicting the warpage. All calculations confirm that a compound thickness ratio of 1.2 results in minimal warpage for a large chip TSOP. In this case, the warpage is reduced to near zero and the compound properties have little influence on warpage. However, for a small chip TSOP, a compound thickness ratio of 2.0–2.9 reduces the warpage. The warpage of small chip TSOP shows a severe saddle shape. The ratio and the magnitude of warpage depend on the compound properties. Also, the elastic method may result in a false simulation.