Cooling Rate Effect on Post Cure Stresses in Molded Plastic IC Packages-Reference-Cited by-同舟云学术

Cooling Rate Effect on Post Cure Stresses in Molded Plastic IC Packages

Published:1998-12-01 Issue:4 Volume:120 Page:385-390
ISSN:1043-7398
Container-title:Journal of Electronic Packaging
language:en
Short-container-title:

Author:

Yi S.¹,Sze K. Y.²

Affiliation:

1. School of Mechanical and Production Engineering, Nanyang Technological University, Singapore, 2263, Republic of Singapore

2. Department of Mechanical Engineering, The University of Hong Kong, Hong Kong

Abstract

Residual stresses during cool down process after curing are evaluated on the basis of thermoviscoelastic finite element analyses with material properties dependent on both time and temperature. Temperature distributions in packages are predicted by solving the heat conduction equations. The effects of cool-down history on thermomechanical responses of a lead-on-chip (LOC), thin small outline package (TSOP) are investigated. Three linear cool down temperature histories are considered. Numerical results show that residual stresses in a LOC TSOP are significantly influenced by the manufacturing temperature history. Residual stresses in plastic packages are strongly time-temperature dependent due to the thermoviscoelastic behavior of molding compounds. Substantial residual stresses arise when a LOC TSOP has cooled to room temperature and rapid cool down permits small viscoelastic effects.

Publisher

ASME International

Subject

Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Link

http://asmedigitalcollection.asme.org/electronicpackaging/article-pdf/120/4/385/5801527/385_1.pdf

Reference10 articles.

1. Amagai M. , SenoH., and EbeK., 1995, “Cracking Failures in Lead-On-Chip Packages Induced by Chip Backside Contamination,” IEEE Trans. on Components, and Manufacturing Technology—Part B, Vol. 18, No. 1, pp. 119–126.

2. Hagen, D., 1992, “Lead-On-Chip TSOP Assembly Process for Fast SRAM With Peripherally Located Bond Ads,” Proc. IEEE Int. Electron. Manufact. Technol. Symp., IEEE, Piscataway, NJ, pp. 39–47.

3. Miura H. , KitanoM., NashimuraA., and KawaiS., 1993, “Thermal Stress Measurement in Silicon Chips Encapsulated in IC Plastic Packages Under Temperature Cycling,” ASME JOURNAL OF ELECTRONIC PACKAGING, Vol. 115, pp. 9–15.

4. Lin K. Y. , and YiS., 1991, “Analysis of Interlaminar Stresses in Viscoelastic Composites,” International Journal of Solids and Structures, Vol. 27, No. 7, pp. 929–945.

5. Pecht M. , WuX., PaikK. W., and BhandarkarS. N., 1995, “To Cut or Not to Cut: A Thermomechanical Stress Analysis of Polyimide Thin-Film on Ceramic Structures,” IEEE Trans. on Components, and Manufacturing Technology—Part B, Vol. 18, No. 1, pp. 150–153.

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Crosslinkable deoxidizing hybrid adhesive of epoxy-diacid for electrical interconnections in semiconductor packaging;Polymer International;2018-06-13

2. Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package;Journal of Electronic Packaging;2010-03-01

3. Evaluation of Residual Stress in Flip Chip Using 3-D Optical Interferometry/FEM Hybrid Technique;Strain;2007-11

4. Deformation Characteristics of Epoxy Compounds for Semiconductor Integrated Circuits;Advanced Materials Research;2006-02

5. Thermal stress induced by the adhesion topology of a semiconductor integrated circuit package;P I MECH ENG L-J MAT;2004