A Model Study of Thermal Stress-Induced Voiding in Electronic Packages

Abstract

Thin film metallizations are one of the most important interconnects in large-scale integrated circuits. They are covered by substrates and passivation films. Large hydrostatic (mean) tension develops due to the constraint and thermal mismatch, and voiding is identified as the failure mechanism. This phenomenon of rapid nucleation and growth of voids is called cavitation instability and it can lead to the failure of ductile components in electronic packages such as metallizations. A micromechanics model is developed to provide the critical mean stress level that will trigger the cavitation instability. It is found that this critical mean stress level the cavitation stress, not only depends on the material properties but also is very sensitive to defects in the material. For example, the cavitation stress decreases drastically as the void volume fraction increases. The stress-based design criterion for ductile components in electronic packages should then be: (1) Von Mises effective stress < yield stress; and (2) mean stress < cavitation stress, which is particularly important to the constrained ductile components in electronic packages such as vias and conductive adhesives. An analytical expression of cavitation stress for elastic-perfectly plastic solids is obtained, and numerical results for elastic-power law hardening solids are presented.