Design technique co-optimization approach to GAA FETs for inverter design at advanced technology node

Abstract

Gate-all-around Nanosheet field-effect transistor (GAA-NSFET) is a potential replacement for the state-of-art FinFET devices at advanced technology nodes. In this article, the impact of process-induced variability such as gate work function variation (WFV) on NSFETs using 3D TCAD numerical device simulation is studied. The WFV of NSFETs and NWFETs using multiple stack channels are also analyzed. The fluctuation in the threshold voltage (σVTH) and on-current (σION) of NSFETs is mainly affected by the WFV of the metal gate. It is investigated that single and 3-stacked NSFET shows superior immunity to WFV compared to NWFET. Furthermore, a layout-based NSFET inverter design using the DTCO technique is followed and the advantages of the stacked NSFET in terms of delay, power dissipation and switching energy are also reported.