Using Vhdl Based Modeling, Synthesis, and Simulation in an Introductory Computer Architecture Laboratory

Abstract

Using VHDL based modelling, synthesis, and simulation in an introductory computer architecture laboratory In many existing curricula, there is a notable lack of recent research advances in CAD tools and rapid prototyping using logic synthesis. This paper describes a novel introductory computer architecture laboratory that utilizes these new developments. VHDL based logic synthesis and timing simulations are used to design a RISC processor.