Affiliation:
1. MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS
02139
Abstract
A method for assessing the benefits of fine-grain paral lelism in "real" programs is presented. The method is based on parallelism profiles and speedup curves de rived by executing dataflow graphs on an interpreter under progressively more realistic assumptions about processor resources and communication costs. Even using traditional algorithms, the programs exhibit ample parallelism when parallelism is exposed at all levels. The bias introduced by the language ld and the compiler is examined. A method of estimating speedup through analysis of the ideal parallelism profile is developed, avoiding repeated execution of programs. It is shown that fine-grain parallelism can be used to mask large, unpredictable memory latency and synchronization waits in architectures employing dataflow instruction execu tion mechanisms. Finally, the effects of grouping por tions of dataflow programs, and requiring that the oper ators in a group execute on a single processor, are explored.
Cited by
12 articles.
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