The Geometrical Effects of Bumps on the Fatigue Life of Flip-chip Packages by Taguchi Method

Abstract

This study employs the coupled field method of thermal analysis with the structural method to simulate the thermal conduction and mechanical behaviors of flip-chip packages. The full, one-quarter symmetrical, one-eighth symmetrical, and stripped finite element models are analyzed by thermal shock test in the temperature loading range of 55–125° C. Engelmaier's model is used to study the issues of fatigue life of these models. The results reveal that the one-eighth symmetrical model can save CPU time, and still retain the accuracy of analysis. Furthermore, this study investigates the geometrical dimensions of bumps regarding the effects and the reliability of flip-chip bumps by means of one-eighth symmetrical finite element model with CAE analysis under the loading of cyclic temperature. The Taguchi method is employed to find the optimum upper diameter, lower diameter, height, and width of bumps in this research. There is a novel concept that the climbing height of underfill is considered as the noise factor since it has an impact on the fatigue life of flip-chip packages. Analysis of variance is used to examine the contribution of these geometric parameters with respect to fatigue life of solder bumps. It is found that the influence of climbing height of underfill is more significant on the fatigue life of flip-chip bumps and the width of the solder bump is the most important factor.