Circle test evaluation of a method of compensating hybrid computing error by predicted integral

Abstract

In a real-time hybrid computing system using an analog and a digital computer joined by ADC and DAC linkage, the continuous analog signals are inevitably sampled and delayed by the ADC-digital computer-DAC execution time. We propose a method of compensating for this error in which the digital computer predicts the integral of the ideal continuous output over each delayed sample period. This predicted integral, then, determines the DAC output having the same integral value over the delayed sample period. Here we have considered only the zero- order hold DAC, but the method is easily extended to other types of hold circuits. The digital prediction algo rithm is based on backward difference extrapolation of the values derived from present and past DAC samples. We tested the effectiveness of this method in a hybrid circle test. Z-transform numerical calculations indicate that sampling rates as low as 20 samples per cycle of oscilla tion and digital execution time as long as 9/10 of a sample period are permissible when backward differences up to the fifth order are used. An actual hybrid circle test with only 10-bit rounded off accuracy in the converters con firmed the effectiveness of the method, even in the pres ence of errors in the analog error range. Using numerical inversion of the z-transform model we computed a number of charts to guide hybriders in select ing a suitable order of the compensation algorithm and sampling frequency. The graphs show the divergence (due to uncompensated time delay) and frequency error (due to loop gain error) as functions of sampling frequency. The parameters for these graphs are digital execution time and the order of the backward difference algorithm.